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PlanAhead Software 13.1
DSP48 DRCs
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DPCA—Checks the DSP48 cascade to ensure it is feasible based on Netlist
connectivity.
DPREG—Checks for DSP48 asynchronous feedback.
FIFO DRC
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FSYN—Checks for synchronous FIFO.
IOB DRC
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IOPCSLR—Checks for part compatibility between monolithic and SLR/SLL devices.
Placer DRCs
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PLCR—Checks that the number of global clocks in a region is less than the value
allowed by the device.
PLCK—Checks all clock placement rules run during the placer.
PLDL—Placement constraint for I/Os that checks whether all I/O are locked and
whether all members of a bus are locked.
PLVP—Checks for non-place-able instances due to resource conflicts or limitations.
RAMB DRC
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RAMB—Checks for clock restrictions for READ_FIRST mode.
Required Pin DRC
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REQP—Checks for required pins that are not connected on instances in the netlist.
Implementation Enhancements
PlanAhead 13 contains the following Implementation enhancements:
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Ease of file ordering for Implementation Runs.
Ability to store Run-specific constraints in a specified UCF file.
Once you implement a design, PlanAhead automatically loads/stores the constraints from
that Run in a run-specific UCF.
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.2)
www.xilinx.com
37
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